The present invention relates to a non-linear extraction circuit and a clock extraction circuit. For instance, these non-linear extraction circuit and clock extraction circuit can be arranged in the clock extraction portion of an optical signal receiver used in the field of optical communication, in order to stably extract a clock pulse from a data signal as it is received.
Heretofore, an optical signal receiver 90 as shown in FIG. 13 of the accompanying drawings has been used for regenerating an original signal from the signal that has been transmitted through an optical fiber, thereby the level of the signal being lowered and the wave form thereof being distorted. This optical signal receiver 90 has three functions, so called, 3R-function, that is, the functions of Reshaping the wave form of the electric signal obtained by the photoelectric conversion by means of an equalizing amplification portion 92, Retiming (or extracting) clock pulses in synchronization with the input data, and then, Regenerating the original signal by means of an identification and regeneration portion 93.
The clock extraction portion 94 arranged in the optical signal receiver 90 includes a non-linear extraction circuit 95 for extracting clock frequency components from the input data, a timing filter 96 for extracting only a fundamental frequency component from the clock frequency components, and a limiting amplification circuit 97 for converting a very small sinusoidal signal into a rectangular signal. This clock extraction portion 94 is required to constantly perform the identification and regeneration operation at the most suitable identification point whatever bit rates may be, and is provided in general with means for optimizing the clock phase.
A non-linear extraction circuit made up of a monostable multivibrator (referred to as xe2x80x9cMono-Multixe2x80x9d hereinafter) and a differential circuit, is disclosed as means for optimizing the clock phase by the JP Patent Publication No. H8(1996)-4261 which is incorporated herein by reference.
According to the circuit configuration disclosed by the JP Patent Publication No. H8(1996)-4261, the clock phase may be optimized. However, in case the duty factor of the input data is made worse, the amplitude spectrum of the extraction timing component is so lowered that there might be a possibility that the output level of the timing filter is lowered. Moreover, in the worst case, there might be a possibility of missing clocks and a generation of clock jitter.
FIG. 14 is a block diagram showing the configuration of a prior art non-linear extraction circuit 100. FIG. 15 is a timing chart indicating the operation of extracting the timing component by the non-linear extraction circuit 100 when the duty factor A/B of the input data signal S70 is made lower than 1 due to the deterioration thereof. As will be seen from the figure, the phase is shifted at every pulse in the repetitive pulses S73 of the timing component. As the results of this, the deterioration is caused in the amplitude spectrum of the timing component.
Therefore, the present invention has been made in view of problems as described above, and the first object of the invention is to provide a non-linear extraction circuit capable of executing the stable extraction of the timing component, even when the duty factor of the input data signal is made worse.
The second object of the invention is to provide a clock extraction circuit to which there is added means for varying output pulse width (referred to as xe2x80x9coutput pulse width varying meansxe2x80x9d hereinafter) to the non-linear extraction circuit.
The third object of the invention is to provide a clock extraction circuit capable of compensating the clock phase variation caused in the constituents making up of the clock extract portion of the optical signal receiver due to the variation in the operational environment, the constituents being the non-linear extraction circuit, the timing filter, and limiting amplifier, and capable of executing the stable extraction of the timing component, thereby optimizing clock phase.
In order to solve such problems as described above, according to the first aspect of the invention, there is provided a non-linear extraction circuit including a differential circuit which differentiates an input data signal at the point of change (rising or falling point or edge) thereof and generates a differential pulse. A first Mono-Multi is connected with the differential circuit and outputs a first pulse signal in synchronization with the differential pulse. A second Mono-Multi is connected with the first Mono-Multi and outputs a second pulse signal in synchronization with the first pulse signal. An OR circuit carries out a logical OR between the first pulse signal and the second pulse signal.
According to the second aspect of the invention, there is provided a clock extraction circuit including a differential circuit which differentiates an input data signal at the point of change (rising or falling point or edge) thereof and generates a differential pulse. A first Mono-Multi is connected with the differential circuit and outputs a first pulse signal in synchronization with the differential pulse. A second Mono-Multi is connected with the first Mono-Multi and outputs a second pulse signal in synchronization with the first pulse signal. An OR circuit carries out a logical OR between the first pulse signal and the second pulse signal. An output pulse width varying means is connected with the OR circuit and variably changes the pulse width of the output pulse signal outputted from the OR circuit.
According to the third aspect of the invention, there is provided a clock extraction circuit in which an output pulse width varying means includes a delay circuit which is connected and delays the output pulse signal from an OR circuit. Further an RS flip-flop circuit is set by the output signal from the OR circuit and is reset by the output signal from the delay circuit.
According to the fourth aspect of the invention, there is provided a clock extraction circuit in which an output pulse width varying means includes a third Mono-Multi which is connected with an OR circuit and outputs the third pulse signal in synchronization with the output pulse signal from the OR circuit.
According to the fifth aspect of the invention, there is provided a clock extraction circuit including a non-linear extraction circuit extracting clock frequency components from an input data signal; a timing filter extracting only a fundamental frequency component from the clock frequency components; a limiting amplifier converting a sinusoidal signal outputted from the timing filter into a rectangular signal; a xc2xd frequency divider for carrying out xc2xd frequency division with respect to the output signal from the limiting amplifier; an EXOR circuit carrying out logical EXOR between the output signal from the xc2xd frequency divider and the input data signal; an average value detector which is connected with the EXOR circuit and detects the average value of the output signal from the EXOR circuit; a comparator comparing the output voltage of the average value detector with a reference voltage Vref, a low-pass filter (LPF) which is connected with the comparator and allows only the low frequency part of the output signal from the comparator to pass; and means for variably changing phase (referred to as xe2x80x9ca phase varying meansxe2x80x9d hereinafter) which is connected with the low-pass filter (LPF) and controls the phase of the output signal from the non-linear extraction circuit.
According to the sixth aspect of the invention, there is provided a clock extraction circuit including a differential circuit which differentiates an input data signal at the point of change thereof and generates a differential pulse; a first Mono-Multi which is connected with the differential circuit and outputs a first pulse signal in synchronization with the differential pulse; a second Mono-Multi which is connected with the first Mono-Multi and outputs the second pulse signal in synchronization with the first pulse signal; an OR circuit carrying out the logical OR between the first pulse signal and the second pulse signal; an output pulse width varying means which is connected with the OR circuit and variably changes the pulse width of the output pulse signal from the OR circuit; a timing filter which is connected with the output pulse width varying means and extracts only a fundamental frequency component from the frequency components of the output signal from the output pulse width varying means; a limiting amplifier which is connected with the timing filter and converts a sinusoidal signal from the timing filter into a rectangular signal; a xc2xd frequency divider for carrying out xc2xd frequency division with respect to the output signal from the limiting amplifier; an EXOR circuit for performing a logical EXOR between the output signal from the xc2xd frequency divider and the input data signal; an average value detector which is connected with the EXOR circuit and detects the average value of the output signal from the EXOR circuit; a comparator comparing the output voltage of the average value detector with a reference voltage Vref; and a low-pass filter (LPF) which is connected with the comparator, allows only the low frequency part of the output signal from said comparator to pass, and supplies the passed to the first Mono-Multi.
According to the seventh aspect of the invention, there is provided a clock extraction circuit in which a first Mono-Multi includes a variable capacitance diode varying the capacitance thereof in response to the voltage applied thereto, and a low-pass filter (LPF) connected with the variable capacitance diode.
According to the eighth aspect of the invention, there is provided a clock extraction circuit including a differential circuit which differentiates an input data signal at the point of change thereof and generates a differential pulse; a first Mono-Multi which is connected with the differential circuit and outputs a first pulse signal in synchronization with the differential pulse; a second Mono-Multi which is connected with the first Mono-Multi and outputs a second pulse signal in synchronization with the first pulse signal; an OR circuit carrying out a logical OR between the first pulse signal and the second pulse signal; an output pulse width varying means which is connected with the OR circuit and variably changes the pulse width of the output pulse signal from the OR circuit; a timing filter which is connected with the output pulse width varying means and extracts only a fundamental frequency component from the frequency components of the output signal from the output pulse width varying means; a limiting amplifier which is connected with the timing filter and converts a sinusoidal signal outputted from the timing filter into a rectangular signal; a 1/(2N) frequency divider for carrying out a 1/(2N) frequency division with respect to the output signal from the limiting amplifier; a 1/N frequency divider for carrying out a 1/N frequency division with respect to the input data signal; an EXOR circuit for carrying out the logical EXOR between the output signal from the 1/(2N) frequency divider and the output signal from the 1/N frequency divider; an average value detector which is connected with the EXOR circuit and detects the average value of the output signal from the EXOR circuit; a comparator comparing the output voltage of the average value detector with a reference voltage Vref; and a low-pass filter (LPF) which is connected with the comparator, allows only the low frequency part of the output signal from the comparator to pass, and supplies the passed to the first Mono-Multi.
According to the ninth aspect of the invention there is provided a clock extraction circuit in which a first Mono-Multi includes a variable capacitance diode varying the capacitance thereof in response to the voltage applied thereto, and a low-pass filter (LPF) connected with the variable capacitance diode.